Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis
نویسندگان
چکیده
This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Details are given on CHDStd-based hierarchy mechanisms and processes required to support Forward Timing-Driven Hierarchical Design capabilities needed for chip design using 0.25u 0.18u technologies and beyond. These capabilities solve some of the key challenges identified by the semiconductor industry’s Design Productivity Crisis. This paper identifies the role of hierarchy for handling difficult chip design information issues and for large complex chip design.
منابع مشابه
CHDStd - A Model for Deep Submicron Design Tools
SEMATECH, a US based consortium of ten major semiconductor manufacturers, is developing a comprehensive system for the design of ICs below .25 μm, which exploits hierarchy, constraint directives, incremental processing, and concurrent design and analysis. This development of SEMATECH's Chip Hierarchical Design System (CHDS) includes major technological investments in algorithms for design pla...
متن کاملA Simple General-purpose I-V Model for All Operating Modes of Deep Submicron MOSFETs
A simple general-purpose I-V model for all operating modes of deep-submicron MOSFETs is presented. Considering the most dominant short channel effects with simple equations including few extra parameters, a reasonable trade-off between simplicity and accuracy is established. To further improve the accuracy, model parameters are optimized over various channel widths and full range of operating v...
متن کاملA global wiring paradigm for deep submicron design
Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance of high-speed integrated circuits. Our previous work has suggested that local interconnect effects can be managed through a deep submicron design hierarchy that uses 50 000 to 100 000 gate modules as primitive building blocks. The primary goal of this paper is to examine global interconnect effec...
متن کاملDesign and Implementation of Low Leakage SRAM Acrhitectures using CMOS VLSI Circuits in Different Technology Environment
There is a demand for portable devices like mobiles and laptops etc. and their long battery life. For high integrity CMOS VLSI circuit design in deep submicron regime, feature size is reduced according to the improved technology. Reduced feature size devices need low power for their operation. Reduced power supply, reduces the threshold voltage of the device. Low threshold devices have improved...
متن کاملA Model for Crosstalk Noise Evaluation in Deep Submicron Processes
To certify the correctness of a design, in deep submicron technologies, the verification process has to cover some new issues. The noise introduced on signals through the crosstalk coupling is one of these emerging problems. In this paper, we propose a model to evaluate the peak value of the noise injected on a signal during the transition of its neighboring signals. This model has been used in...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1998